(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of attaching the heat spreader of a PBGA package by attaching the copper pads to a non-external ground.
(2) Description of the Prior Art
The semiconductor industry has for many years achieved semiconductor device product improvements by device miniaturization and by increasing the device packaging density. Increased device density is typically implemented internally to the device, by creating device features of smaller dimensions. For devices that must be assembled into complete device packages, the completed semiconductor devices are frequently assembled in multi-device packages. This has led to the field of high density interconnect technology, mounting multilayer structures on the surface of a substrate and connecting integrated circuits to one another. This approach results in high wiring and high packaging density, whereby many integrated circuit chips are physically and electrically interconnected and connected to a single substrate commonly referred to as a multi-chip module (MCM). Electrical device isolation is provided by layers of dielectric, such as polyimide, that separate various functional planes (such as signal lines, power lines and ground planes) in the substrate. Metal interconnects can readily be provided by metal lines that are embedded in other layers of dielectric, thereby using vias (holes) to provide electrical connections between the interconnect lines. Interconnect lines must thereby be connected in such a manner that optimum performance can be realized for the completed package. For instance, adjacent layers must be formed such that primary signal propagation directions are orthogonal to each other. This is done in order to avoid crosstalk between lines that are in close physical proximity, which can induce false signals and noise between adjacent lines. Good planarity must also be maintained between adjacent layers of interconnect lines because the metal interconnect lines are typically narrow in width and thick in a vertical direction (in the range of 5 to 10 microns thick) and must be patterned with microlithography. Patterned layers must therefore be substantially flat and smooth (i.e. have good planarity) so that these layers can serve as a base for the next layer.
One of the original approaches that has been used to create surface mounted, high pin count integrated circuit packages has been the use of Quad Flat Packs (QFP's) with various pin configurations. For QFP's, closely spaced leads along the four edges of the flat package are used for making electrical connections from where the electrical connections are distributed to the surrounding circuitry. The input/output connections that can be made to QFP packages are therefore confined to the edges of the flat package, which limits the number of I/O connections that can be made to the QFP even in applications where the pin to pin spacing is small. QFP's have found to be cost effective for semiconductor devices where the device I/O pin count does not exceed 200. To circumvent this limitation, a new package, a Ball Grid Array (BGA) package has been introduced. For the BGA package, the electrical contact points are distributed over the entire bottom surface of the package, thereby eliminating the restriction of having I/O connects only around the periphery of the package. More contact points with greater spacing between the contact points can therefore be allocated across the BGA package than was the case with the QFP's. The contact points that are used for the BGA package are typically solder balls that have the added advantage of facilitating flow soldering of the package onto a printed circuit board.
A Ball Grid Array (BGA) is an array of solderable balls placed on a chip carrier, such as a Printed Circuit Board (PCB). The balls contact a printed circuit board in an array configuration where, after reheat, the balls connect the chip to the printed circuit board. BGA's are known with 40, 50 and 60 mils spacings in regular or staggered array patterns. The BGA package is part of a larger packaging approach that is often referred to as Chip Scale Packages (CSP), which is a packaging approach that is considered to be different from the previously highlighted approach of MCM's.
Flip Chip packages have in general been used to accommodate increased I/O count combined with increased high requirements for high performance IC's. Flip chip technology fabricates bumps (typically Pb/Sn solder) on Al pads and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package through the shortest paths. This approach can be applied to single-chip packaging and to higher integrated levels of packaging (in which the packages are larger) and to more sophisticated packaging media that accommodate several chips to form larger functional units.
For the packaging of semiconductor devices, the package in which the devices are contained provides protection of the device from environmental influences such as mechanical damage or damage caused by moisture affecting exposed surfaces of the device. Part of the package design includes the design of electrically conductive interfaces that enable the device to be electrically interconnected with surrounding circuitry. Increased device density has not only created new demands for input/output connections of the device but has also caused considerable more thermal energy to be expanded per cubic volume content of the device, resulting in increased demands on methods of heat exchange between the device and its surrounding and supporting surfaces. In many of the semiconductor device packages, the device is mounted in close physical proximity to a heat sink combined with methods, such as connections of low resistance to thermal heat conductivity, are implemented as part of the package.
It is therefore the objective of providing a package for semiconductor devices, such as flip chips, that has a direct ground connect between the device and a heatsink on the surface of which the device is mounted. In a typical device packaging arrangement, a substrate layer that contains for instance three layers of interconnects, is used to connect the device to surrounding circuitry. Electrical connections are made between the flip chip and the substrate layers. Contact points provided in or on the surface of the device make contact with contact points in the top surface of the substrate layer, the substrate layer re-distributes (fan-out) the device contact points. One of the approaches that has been used to create high thermal interchange between the device and the heatsink is to create one or more openings in the substrate layers. These openings are filled with a low-resistivity material, establishing electrical contact between one selected copper pad of the copper traces (in the upper layer of the substrate layer) and the heatsink. Connecting the ground point of the IC die to a selected copper pad of metal (for instance copper) traces completes the ground path between the ground of the IC die and the heatsink. A molding is typically encased between the lower surface of the device and the upper surface of the substrate. This molding is referred to as underfill since it is filled in under the original semiconductor device. A heat sink is typically attached to the lower surface of the device.
FIG. 1 shows an example of a Prior Art method of packaging a BGA/flip chip whereby a major part of the package is a heatsink 40. The semiconductor chip or die 42 takes up the center of the package; contact points to die 42 are closely spaced around the periphery of die 42. Cavity 46 is provided in the heatsink 40 for the mounting of the Integrated Circuit (IC) chip 42. Heatsink 40 has a surface that is electrically conductive. The top of the IC chip 42 is in close physical contact with the heatsink 40 via a thin adhesive layer 48 of thermally conductive epoxy that is deposited over the bottom surface of cavity 46, the IC die 42 is attached to the heatsink 40 by means of this layer 48. The adhesive layer 48 is cured after the IC die 42 has been inserted into cavity 46. The contact points of the die 42 are conductively bonded, using wire-bonding techniques, to the substrate layer 50.
The bond wires 58 and 60 are shown here as applied for the connection of IC die 42 to layer 56 of the substrate 50. The substrate 50 has been shown as containing three layers, that is layers 52, 54 and 56. Layer 52 is typically an adhesive layer that directly connects the substrate layer 50 to the heatsink 40. This establishes the necessary mechanical support for the wire bonding operation. Layer 54 can contain a stiffener that provides rigidity to the substrate layer 50, layer 56 contains copper traces that further interconnect the solder balls 62 to the surrounding circuitry. Wires 58 and 60 provide wire bond connections between contact points (not shown) on the IC die 42 and copper traces contained in layer 56 of the substrate layer 50.
The substrate layer 50 contains, as has previously been indicated, adhesive layer 52, layer 54 of stiffener for the substrate layer and copper traces in layer 56 for interconnect of the IC die 42. In addition, a solder mask layer 57 (typically a layer of dielectric) with openings is deposited over the surface of substrate layer 50, the openings in solder mask 57 expose the copper traces in layer 56 to provide solder connections between the copper traces of layer 56 and the contact balls 62.
FIG. 1 also shows how the IC die 42 is encapsulated using an encapsulation material 64 that is syringe dispensed to surround die 42, forming the encapsulation layer 64. It must be noted that this layer not only surrounds the IC die 42 but also covers the bond wires 58 and 60. The encapsulation layer 64 is cured after injection.
Other methods of encapsulating a semiconductor device provide a heatsink that overlays the semiconductor device. The semiconductor device is mounted on the surface of a substrate by means of a layer of epoxy. Gold bond wires can connect electrical contact points that are provided in the upper surface of the device to the substrate, contact balls are provided in or on the lower surface of the device for additional connections (typically for high frequency signal transfer) between the device and the substrate. A molding compound is used to encapsulate the die and the bond wires, providing environmental protection to the die. By making high heat conductivity connections between the bottom of the die, heat generated in the die can be transferred from the die to the substrate. For applications where additional heat must be removed from the semiconductor die, the molding compound that encapsulates the die can be partially removed from above the upper surface of the die, partially exposing this upper surface. This exposed portion of the upper surface of the die can then be brought in direct physical contact with a heatsink that overlays the semiconductor die. The heatsink is typically formed such that it can also be attached to the underlying substrate, resulting in a mechanically strong package. Where necessary, the heat sink in turn can be encapsulated in a molding compound that is now formed overlying the upper surface of the package, the largest area of contact between the molding compound and the package being the upper surface of the heatsink.
The invention addresses aspects of attachment of a semiconductor device to a heatsink. The invention provides a method that simplifies this attachment.
U.S. Pat. No. 5,977,626 (Wang et al.) teach a heat spreader for a PBGA.
U.S. Pat. No. 6,020,637 (Karnezos) shows a removable heat spreader for a package.
U.S. Pat. No. 6,011,304 (Mertol) teaches a heat spreader for a cavity down BGA.
U.S. Pat. No. 5,903,052 (Chen et al.) show a heat spreader attached to the bottom of a substrate. However, this reference differs from the invention.
U.S. Pat. No. 5,847,929 (Bernier et al.) show a method for a heatsink.
U.S. Pat. No. 5,371,404 (Juskey et al.) show a method where the ground acts as part of a heatsink/shield.